T. Kaiser and F. Gerfers, “A 2.41-µW/MHz, 437-PE/mm² CGRA in 22 nm FD-SOI with RISC-Like Code Generation,” presented at 2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL Chips), Tokyo, Japan, April 2023 (paper, doi).
M. Runge, J. Edler, T. Kaiser, K. Misselwitz and F. Gerfers, “An 18-MS/s 76-dB SNDR Continuous-Time ΔΣ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter,” in IEEE Journal of Solid-State Circuits, February 2023 (doi).
2022
T. Kaiser and F. Gerfers, “Pasithea-1: An Energy-Efficient Self-Contained CGRA With RISC-Like ISA,” presented at 35th GI/ITG International Conference on Architecture of Computing Systems (ARCS), September 2022 (paper, doi).
E. Wittenhagen, P. Kurth, T. Kaiser and F. Gerfers, “A TI 12 GS/s Sampled Beam-Forming Receiver for a 2×2 Antenna-Array with 69 dBc SFDR,” presented at 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), October 2022 (doi)
M. Runge and J. Edler and D. Schmock and T. Kaiser and F. Gerfers, “A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS 2022,” presented at IEEE Custom Integrated Circuits Conference (CICC), April 2022 (doi).
2021
M. Runge and J. Edler and T. Kaiser and F. Gerfers, “A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS,” presented at 2021 IEEE Custom Integrated Circuits Conference (CICC), April 2021 (doi)
M. Runge and J. Edler and T. Kaiser and F. Gerfers, “A 0.9 V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6 fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS,” presented at 2021 IEEE Custom Integrated Circuits Conference (CICC), April 2021 (doi)
2020
T. Kaiser and F. Gerfers, “Towards pW-Class IoT Nodes using Crystalline Oxide Semiconductor Dynamic Logic,” presented at 2020 IEEE International Symposium on Circuits and Systems (ISCAS), October 2020 (paper, doi).